1. Field of the Invention
The present invention relates to flash memory, and more particularly to sense amplifiers for flash memory.
2. Description of Related Art
FIG. 1 is a high-level functional block diagram of a conventional sense amplifier 10 suitable for nonvolatile memory technologies such as flash memory. The sense amplifier 10 has two branches, a reference cell current branch 20 and a main cell current branch 40. In the reference cell current branch 20, a reference cell 26 determines a reference cell current, a column load 22 converts the reference cell current to a voltage VRC, and a drain bias 24 maintains the drain voltage for the reference cell 26 at an appropriate level. In the main cell current branch 40, a main cell 46 operationally selected from an array of flash memory cells determines a main cell current based on the data stored therein, a column load 42 converts the main cell current to a voltage VMC, and a drain bias 44 maintains the drain voltage for the selected memory cell at an appropriate level. A differential amplifier 30 compares the reference cell voltage VRC with the main cell voltage VMC and furnishes a logical level at its output depending on the relative values of VRC and VMC.
Many different circuits and devices may be used for the column loads 22 and 42, for the drain bias 24 and 44, for the reference cell 26, for the array of main cells 46, and for the differential amplifier 30. FIGS. 2 and 3 show two different implementations.
FIG. 2 is a schematic diagram of a conventional sense amplifier 110 which is based on the approach shown in FIG. 1. The sense amplifier 110 has two branches, a reference cell current branch 120 and a main cell current branch 140. In the reference cell current branch 120, a reference cell 129 determines the reference cell current, and a MOSFET load 125 converts the reference cell current to a voltage RIN. A drain bias circuit, which maintains the drain voltage for the reference cell 129 at an appropriate level, is formed by MOSFET's 122, 123 and 126. Additional MOSFET's in the reference cell current branch 120 include a reference YB select transistor 127, a reference YA select transistor 128, and the reference cell 129 whose gate is connected to a reference wordline. In the main cell current branch 140, a main cell 149 selected from the flash memory array determines the main cell current, and a MOSFET load 145 converts the main cell current to a voltage SIN. A drain bias circuit, which maintains the drain voltage for the main cell 149 at an appropriate level, is formed by MOSFET's 142, 143 and 146. Additional MOSFET's in the main cell current branch 140 include a YB select transistor 147, a YA select transistor 148, and the main cell 149 whose gate is connected to a memory array wordline. A differential amplifier 130 compares the reference cell voltage RIN with the main cell voltage SIN and furnishes a logical level at its DATA output depending on the relative values of RIN and SIN.
The sense amplifier 110 operates as follows. The reference cell current in the reference cell current branch 120 is established by the reference YB select transistor 127, the reference YA select transistor 128, and in particular the reference cell 129. The voltage RIN is established by flow of the reference cell current through the MOSFET load 125. A predetermined drain voltage is established at the drain of the reference cell 129.
The main cell current in the main cell current branch 140 is established by the YB select transistor 147, the YA select transistor 148, and in particular the main cell 149 selected from an array of flash memory cells. If the main cell 149 has no charge on its gate, which corresponds to a logical one, the main cell 149 conducts heavily and the main cell current is large. The voltage SIN tends to go low due to a high voltage drop across the MOSFET load 145, but the voltage drop across the transistor 146 is appropriately low for establishing the predetermined drain voltage at the drain of the main cell 149. On the other hand, if the main cell 149 has a negative charge on its gate, which corresponds to a logical zero, the main cell 149 conducts weakly if at all and the main cell current becomes small or zero. The voltage SIN tends to go high due to a small voltage drop across the MOSFET load 145, but the voltage drop across the transistor 146 is appropriately high for establishing the predetermined drain voltage at the drain of the main cell 149.
The voltages RIN and SIN are applied to the positive and negative inputs respectively of the differential amplifier 130. The output DIGITAL DATA of the differential amplifier 130 represents either a logical zero or logical one depending on the relative values of RIN and SIN.
FIG. 3 is a schematic diagram of another conventional sense amplifier 210 which is also based on the approach shown in FIG. 1. The sense amplifier 210 has two branches, a reference cell current branch 220 and a main cell current branch 240. In the reference cell current branch 220, a reference cell 228 determines the reference cell current, and a resistive load 221 converts the reference cell current to a voltage RIN. A drain bias circuit, which maintains the drain voltage for the reference cell 228 at an appropriate level, is formed by MOSFET's 222, 224 and 225. MOSFET 223 is a quick charge transistor for the bit line. Additional MOSFET's in the reference cell current branch 220 include a mini-array W-select transistor 226, a mini-array Y-select transistor 227, and the reference cell 228 whose gate is connected to a mini-array wordline. In the main cell current branch 240, a main cell 248 selected from a flash memory array determines the main cell current, and a resistive load 241 converts the main cell current to a voltage SIN. A drain bias circuit, which maintains the drain voltage for the main cell 248 at an appropriate level, is formed by MOSFET's 242, 244 and 245. MOSFET 243 is a quick charge transistor for the bit line. Additional MOSFET's in the main cell current branch 240 include a W-select transistor 246, a Y-select transistor 247, and a selected main cell 248 whose gate is connected to an array wordline. A differential amplifier 230 compares the reference cell voltage RIN with the main cell voltage SIN and furnishes a logical level at its DIGITAL DATA output depending on the relative values of RIN and SIN.
FIG. 4 is a graph of illustrative drain current ID versus gate voltage VGATE in the sense amplifier 210, for an erased main cell, for a reference cell, and for a programmed main cell. For a read gate voltage of 5 volts, the drain current Id is zero for a programmed cell and somewhat in excess of 100 μA for an erased cell. Since the drain current Id is 50 μA for the reference cell, the sense amplifier 210 can readily distinguish the over 100 μA current attributable to an erased cell from the zero current attributable to a programmed cell. These values are illustrative, since actual values depend on the specific implementation and component values selected.